1. Field of the Invention
The invention generally relates to broadcast scan, and, more particularly, to a method for efficiently inserting scan elements into scan chains to reduce or eliminate bit collisions.
2. Description of the Related Art
Scan testing of circuits is accomplished by connecting scan elements (i.e., latches or flip-flops) in series in a test path so that the output of each scan element is fed to the input of the next scan element in the scan chain. Each test pattern is shifted in to the scan chain via a scan-in pin. Then, the test pattern from the scan element in the scan chain is shifted in to a cone of logic (i.e., a combination logic in a circuit that resolves to a single point) under test. In a broadcast scan technique, each scan-in pin is fanned out to multiple scan chains. That is, each test pattern that is scanned into the chip via a single scan-in pin passes through multiple scan chains. Thus, the same values (e.g., 0 or 1) appear at the inputs of the set of scan chains that receive their data from the same scan-in pin. This technique has been shown to reduce test data volume and test time. However, using this technique may cause test coverage to suffer.
Specifically, when using the broadcast scan technique, the input received by each scan element (i.e., latch or flip-flop) at the same sequential position on different scan chains that receive a test pattern from the same scan-in pin will necessarily have the same value. Collisions can occur if the values required to be scanned-in to test a certain cone of logic must be different. That is, if the logic-under-test requires opposite values on two scan elements that are at the same sequential position on two parallel scan chains that fan out from the same scan-in pin, there will be a collision. This collision may make it harder to generate tests for a fault and may cause the test coverage to suffer.
Several solutions for the problem are known. For example, after test patterns have been applied using the broadcast scan technique, clean-up patterns using full scan (p=1) can be applied to test untested faults. However, these clean-up patterns increase test data volume and test time, thereby, defeating the purpose of using the broadcast scan technique. Alternatively, scan chains can be inserted such that all the scan elements in a certain core or module appear on the same scan chain in the hope that a section of logic will be able to receive opposite values on different input scan elements. However, even if all inputs of a core are on the same scan chain, this ad hoc method cannot be proven to minimize collisions of scan elements, since it is an optimistic guess at best and ensuring that all internal elements of a core lie on the same short scan chain is impossible.
Therefore, there is a need in the art for an improved broadcast scan technique that maximizes test coverage and, more particularly, for a method of efficiently inserting scan elements (i.e., latches or flip-flops) into scan chains to reduce or completely eliminate bit collisions.